Questionable Design Choices

Signal Stories

Blog posts, bench notes, debugging stories, software work, FRC notes, and signal-processing writeups.

TALU: 16-bit Custom RISC Processor

TALU is a custom 16-bit RISC-style processor designed in Logisim with its own instruction set, ALU, instruction register, decoder/control...

SAGE Penrose / APX

SAGE is a chip series, Penrose is its architecture, and APX is the Adaptive Pathway eXecutor. The research investigates selective activat...

Naval Research Paper

This is a long-term naval research archive entry. Its exact title and scope were not recovered, so it is intentionally presented without ...

Naval Dipping Sonar Prototype

A hands-on embedded-systems build investigating sonar pulse generation, propagation, return detection, analog conditioning, timing, and v...

FIDELIS Hardware Security Superchip

FIDELIS is a research architecture for a hardware-security coprocessor that models computational reality and causal execution to detect v...

Digital Electronics CPU Labs

A series of digital-electronics labs using Logisim-style circuit construction to build CPU datapaths from ALUs, registers, memory, and in...

DE10-Nano FPGA Compute Block

A modular FPGA compute, sensing, and display platform built around the DE10-Nano for experiments in hardware acceleration, signal capture...

Sonar Pulse Timing Captures

Notes on measuring sonar pulse timing, filtering noisy captures, and deciding what belongs in firmware versus post-processing.

FPGA Bring-Up Notes

Bringing up a custom FPGA board or soft-core microcontroller block requires structured verification: starting from clock distribution con...

Why Did This Work?

A debugging note for the fixes that should not have worked, the measurements that proved they did, and the cleanup required after the sur...

Parkinson Tremor Detection

Detection and Analysis of Hand Tremors Using Gyroscopic and Accelerometric Data for Early Parkinson’s Disease Indication